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  HD61200 (lcd driver with 80-channel outputs) description the HD61200 is a column driver lsi for a large- area dot matrix lcd. it employs 1/32 or more duty cycle multiplexing method. it receives serial display data from a micro controller or a display control lsi, hd61830, etc., and generates liquid crystal driving signals. features liquid crystal display driver with serial/parallel conversion function internal liquid crystal display driver: 80 drivers drives liquid crystal panels with 1/32?/128 duty cycle multiplexing can interface to lcd controllers, hd61830 and hd61830b data transfer rate: 2.5 mhz max power supply: v cc : 5 v 10% (internal logic) power supply voltage for liquid crystal display drive: 8 v to 17 v cmos process ordering information type no. package HD61200 100-pin plastic qfp (fp-100) free datasheet http://www..net/
pin arrangement HD61200 193 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 y51 y52 y53 y54 y55 y56 y57 y58 y59 y60 y61 y62 y63 y64 y65 y66 y67 y68 y69 y70 y71 y72 y73 y74 y75 y76 y77 y78 y79 y80 y31 y32 y33 y34 y35 y36 y37 y38 y39 y40 y41 y42 y43 y44 y45 y46 y47 y48 y49 y50 y30 y29 y28 y27 y26 y25 y24 y23 y22 y21 y20 y19 y18 y17 y16 y15 y14 y13 y12 y11 y10 y9 y8 y7 y6 y5 y4 y3 y2 y1 v ee v 1l v 2l v 3l v 4l gnd cl1 fcs shl cl2 dl dr e m car v cc v 4r v 3r v 2r v 1r (top view) free datasheet http://www..net/
block diagram 194 HD61200 12345678 77 78 79 80 liquid crystal display driver circuit 80 12345678 77 78 79 80 latch circuit 2 80 bits 80 12345678 77 78 79 80 latch circuit 1 4 bit 20 selector 12 20 ?1 ?2 ?20 5 counter s sr eef/f test input s/p control circuit v cc gnd v ee car m cl1 dl dr shl cl2 e fcs v 1l v 2l v 3l v 4l y1 y2 y80 v 1r v 2r v 3r v 4r 4 free datasheet http://www..net/
HD61200 195 block function liquid crystal display driver circuit the combination of the data from the latch circuit 2 and m signal causes one of the 4 liquid crystal driver levels, v1, v2, v3, and v4 to be output. 80-bit latch circuit 2 the data from latch circuit 1 is latched at the fall of cl1 and output to liquid crystal display driver circuit. s/p serial/parallel conversion circuit which converts 1- bit data into 4-bit data. when shl is low level, data from dl is converted into 4-bit data and transferred to the latch circuit 1. in this case, dont connect any lines to terminal dr. when shl is high level, input data from terminal dr without connecting any lines to terminal dl. 80-bit latch circuit 1 the 4-bit data is latched at ? to ?0 and output to latch circuit 2. when shl is low level, the data from dl are latched in order of 1 ? 2 ? 3 ? ... 80 of each latch. when shl is high level, they are latched in a reverse order (80 ? 79 ? 78 ? ... 1). selector the selector decodes output signals from the counter and generates latch clock ? to ?0. when the lsi is not active, ? to ?0 are not generated, so the data at latch circuit 1 is stored even if input data (dl, dr) changes. control circuit controls operation: when e?/f (enable f/f) indicates 1, s/p conversion is started by inputting low level to e . after 80-bit data has been all converted, car output turns into low level and e?/f is reset to 0, and consequently the conversion stops. e?/f is rs flip-flop circuit which gives priority to set over reset and is set at high level of cl1. the counter consists of 7 bits, and the output signals upper 5 bits are transferred to the selector. car signal turns into high level at the rise of cl1. the number of bits that can be s/p-converted can be increased by connecting car terminal with e terminal of the next HD61200. free datasheet http://www..net/
terminal functions description terminal number of connected name terminals i/o to functions v cc 1 power v cc ?gnd: power supply for internal logic gnd 1 supply v cc ?v ee : power supply for lcd drive circuit v ee 1 v 1l ? 4l 8 power power supply for liquid crystal drive. v 1r ? 4r supply v 1l (v 1r ), v 2l (v 2r ): selection level v 3l (v 3r ), v 4l (v 4r ): non-selection level power supplies connected with v 1l and v 1r (v 2l & v 2r , v 3l & v 3r , v 4l & v 4r ) should have the same voltages. y1?80 80 o lcd liquid crystal driver outputs. selects one of the 4 levels, v1, v2, v3, and v4. relation among output level, m, and display data (d) is as follows: m 1 1 controller switch signal to convert liquid crystal drive waveform into ac. cl1 1 i controller synchronous signal (a counter is reset at high level). latch clock of display data (falling edge triggered). synchronized with the fall of cl1, liquid crystal driver signals corresponding to the display data are output. cl2 1 i controller shift clock of display data (d). falling edge triggered. dl, dr 2 i controller input of serial display data (d). liquid crystal liquid crystal (d) driver output display 1 (high level) selection level on 0 (low level) non-selection level off 196 HD61200 m d output level 10 1010 v1 v3 v2 v4 free datasheet http://www..net/
terminal number of connected name terminals i/o to functions shl 1 i v cc or gnd selects the shift direction of serial data. when the serial data (d) is input in order of d1 ? ... ? d80, the relations between the data (d) and output y are as follows: shl y1 y2 y3 ... y80 low d1 d2 d3 ... d80 high d80 d79 d78 ... d1 when shl is low, data is input from the dl terminal. no lines should be connected to the dr terminal. when shl is high, the relation between dl and dr reverses. e 1 i gnd or the controls the s/p conversion. terminal the operation stops on high level, and the s/p car of the conversion starts on low level. HD61200 car 1 o input used for cascade connection with the HD61200 to terminal e increase the number of bits that can be s/p of the converted. HD61200 fcs 1 i gnd input terminal for test. connect to gnd. HD61200 197 free datasheet http://www..net/
198 HD61200 operation of the HD61200 the following describes an lcd panel with 64 240 dots on which characters are displayed with 1/64 duty cycle dynamic drive. figure 1 is an example of liquid crystal display and connection to HD61200s. figure 2 is a time chart of HD61200 i/o signals. figure 1 lcd driver with 64 240 dots e shl fcs m cl1 cl2 dl dr car y1 y2 y80 HD61200 (no. 1) open e shl fcs m cl1 cl2 dl dr car y1 y2 y80 HD61200 (no. 2) open e shl fcs m cl1 cl2 dl dr car y1 y80 HD61200 (no. 3) open open com1 com2 com3 com63 com64 m cl1 cl2 data lcd panel (64 240 dots) 1, 1 2, 1 3, 1 1, 2 2, 2 3, 2 1, 80 2, 80 3, 80 1, 81 2, 81 1, 82 2, 82 1, 160 2, 160 1, 161 2, 161 1, 240 2, 240 3, 240 63, 1 64, 1 63, 2 64, 2 63, 80 64, 80 64, 81 64, 82 64, 160 63, 240 64, 240 cascade three HD61200s. input data to the dl terminal of no. 1, no. 2, and no. 3. connect e of no. 1 to gnd. dont connect any lines to car of no. 3. connect common signal terminals (com1Ccom64) to x1Cx64 of common driver hd61203. (m, n) of lcd panel is the address corresponding to each dot. timing chart for the example of connection, dl input (m, n) in this figure is the data that corresponds to each address (m, n) of lcd panel. free datasheet http://www..net/
figure 2 h61200 timing chart HD61200 199 1,1 2,1 3,1 4,1 5,1 6,1 1,2 2,2 3,2 4,2 5,2 6,2 1,80 2,80 3,80 4,80 5,80 6,80 1,240 2,240 3,240 4,240 5,240 6,240 60,1 61,1 62,1 63,1 64,1 60,2 61,2 62,2 63,2 64,2 60,80 61,80 62,80 63,80 64,80 60,240 61,240 62,240 63,240 64,240 1, 1 1, 2 1, 3 1, 238 1, 237 1, 239 1, 240 2, 1 2, 2 2, 3 2, 238 2, 237 2, 239 2, 240 3, 1 3, 2 3, 3 3, 4 82, 238 82, 237 82, 239 82, 240 83, 1 83, 2 83, 3 83, 4 83, 238 83, 237 83, 239 83, 240 84, 1 84, 2 84, 3 84, 238 84, 237 84, 239 84, 240 1 frame e (no. 2) e (no. 3) m cl1 cl2 y1Cy80 car (no. 1) car (no. 2) car (no. 3) dl m cl1 cl2 dl m cl1 y1 (no. 1) y1Cy80 y2 (no. 1) y80 (no. 1) y80 (no. 3) to to timing chart for horizontal direction timing chart for vertical direction timing chart for liquid crystal display driver output 1,1 1,2 1,3 1,76 1,77 1,78 1,79 1,80 1,81 1,82 1,83 1,156 1,157 1,158 1,159 1,160 1,161 1,162 1,163 1,236 1,237 1,238 1,239 1,240 free datasheet http://www..net/
200 HD61200 application example the liquid crystal panel is divided into upper and lower parts. these two parts are driven separately. HD61200s no. 1 to no. 3 drive the upper half. serial data, which are input from the data(1) terminal, appear at y 1 ? y 2 ? ... y 80 terminal of no. 1, then at y 1 ? y 2 ? ... y 80 of no. 2 and then at y 1 ? y 2 ? ... y 80 of no. 3 in the order in which they were input (in the case of shl = low). HD61200s no. 4 to no. 6 drive the lower half. serial data, which are input from data(2) terminal, appear at y 80 ? y 79 ? ... y 1 of no. 4, then at y 80 ? y 79 ? ... y 1 of no. 5 and then y 80 ? y 79 ? ... y 1 of no. 6 in the order in which they were input (in the case of shl = high). as shown in this example, a pc board for display divided into upper and lower half can be easily designed by using shl terminal effectively. figure 3 example of 128 240 dot liquid crystal display (1/64 duty cycle) e shl fcs m cl1 cl2 dl dr car y1 y80 HD61200 no. 1 e shl fcs m cl1 cl2 dl dr car HD61200 no. 4 y1 y80 e shl fcs m cl1 cl2 dl dr car y1 y80 HD61200 no. 2 e shl fcs m cl1 cl2 dl dr car HD61200 no. 5 y1 y80 e shl fcs m cl1 cl2 dl dr car y1 y80 HD61200 no. 3 e shl fcs m cl1 cl2 dl dr car HD61200 no. 6 y1 y80 v cc v cc v cc data (1) m cl1 cl2 data (2) 240 dots upper panel (64 dots) lower panel (64 dots) free datasheet http://www..net/
absolute maximum ratings item symbol value unit note supply voltage (1) v cc ?.3 to +7.0 v 2 supply voltage (2) v ee v cc ?19.0 to v cc + 0.3 v terminal voltage (1) v t1 ?.3 to v cc + 0.3 v 2, 3 terminal voltage (2) v t2 v ee ?0.3 to v cc + 0.3 v 4 operating temperature t opr ?0 to +75 ? storage temperature t stg ?5 to +125 ? notes: 1. lsis may be permanently destroyed if being used beyond the absolute maximum ratings. in ordinary operation, it is desirable to use them within the limits of electrical characteristics, because using them beyond these conditions may cause malfunction and poor reliability. 2. all voltage values are referenced to gnd = 0 v. 3. applies to input terminals, fcs, shl, cl1, cl2, dl, dr, e, and m. 4. applies to v 1l , v 1r , v 2l , v 2r , v 3l , v 3r , v 4l , and v 4r . must maintain v cc 3 v 1l = v 1r 3 v 3l = v 3r 3 v 4l = v 4r 3 v 2l = v 2r 3 v ee . connect a protection resistor of 15 10% to each terminal in series. HD61200 201 free datasheet http://www..net/
electrical characteristics dc characteristics (v cc = 5 v 10%, gnd = 0 v, v cc ?v ee = 8 v to 17 v, ta = ?0 to 75?) item symbol min typ max unit test condition note input high voltage v ih 0.7 v cc ? cc v1 input low voltage v il 0 0.3 v cc v1 output high voltage v oh v cc ?0.4 v i oh = ?00 a 2 output low voltage v ol 0.4 v i ol = 400 a 2 driver on resistance r on 7.5 k load current = 5 100 a input leakage current i il1 ? 1 a v in = 0 to v cc 1 input leakage current i il2 ? 2 a v in = v ee to v cc 3 dissipation current (1) i gnd 1.0 ma 4 dissipation current (2) i ee 0.1 ma 4 notes: 1. applies to cl1, cl2, shl, e , m, dl, and dr. 2. applies to car . 3. applies to v 1l , v 1r , v 2l , v 2r , v 3l , v 3r , v 4l , and v 4r . 4. specified when display data is transferred under following conditions: cl2 frequency f cp2 = 2.5 mhz (data transfer rate) cl1 frequency f cp1 = 4.48 khz (data latch frequency) m frequency f m = 35 hz (frame frequency/2) specified at v ih = v cc (v), v il = 0 v and load on outputs. i gnd : currents between v cc and gnd. i ee : currents between v cc and v ee . 5. resistance between terminal y and terminal v (one of v 1l , v 1r , v 2l , v 2r , v 3l , v 3r , v 4l , and v 4r when load current flows through one of the terminals y1 to y80. this value is specified under the following condition: 202 HD61200 terminal y (y1?80) v 1l , v 1r v 3l , v 3r v 4l , v 4r v 2l , v 2r ron v cc ?v ee = 17 v v 1l = v 1r , v 3l = v 3r = v cc ?2/7 (v cc ?v ee ) v 2l = v 2r , v 4l = v 4r = v ee + 2/7 (v cc ?v ee ) free datasheet http://www..net/
HD61200 203 the following here is a description of the range of power supply voltage for liquid crystal display drivers. apply positive voltage to v 1l = v 1r and v 3l = v 3r and negative voltage to v 2l = v 2r and v 4l = v 4r within the d v range. this range allows stable impedance on driver output (ron). notice the d v depends on power supply voltage v cc ? ee . d v d v v cc v1 (v 1l = v 1r ) v3 (v 3l = v 3r ) v4 (v 4l = v 4r ) v2 (v 2l = v 2r ) v ee 5.5 3 d v (v) 817 v cc e v ee (v) range of power supply voltage for liquid crystal display drive correlation between driver output waveform and power supply voltage for liquid crystal display drive correlation between power supply voltage v cc e v ee and d v free datasheet http://www..net/
terminal configuration 204 HD61200 pmos v cc nmos applicable terminals: cl1, cl2, shl, e , m pmos v cc nmos pmos v cc enable applicable terminals: dl, dr input terminal (with enable) input terminal output terminal dl dr shl pmos nmos v cc applicable terminal: car output terminal v cc pmos v 1l , v 1r v cc pmos v 3l , v 3r v ee nmos v 4l , v 4r v ee nmos v 2l , v 2r applicable terminals: y1Cy80 free datasheet http://www..net/
ac characteristics (v cc = 5 v 10%, gnd = 0 v, ta = ?0 to +75?) item symbol min typ max unit test condition note clock cycle time t cyc 400 ns clock high level width t cwh 150 ns clock low level width t cwl 150 ns clock setup time t scl 100 ns clock hold time t hcl 100 ns clock rise/fall time t ct 30 ns clock phase different time t cl 100 ns data setup time t dsu 80 ns data hold time t dh 100 ns e setup time t esu 200 ns output delay time t dcar 300 ns 1 m phase difference time t cm 300 ns note: 1. the following load circuit is connected for specification: HD61200 205 test point 30 pf t ct t ct t cwh v ih v il t scl t cl t hcl t cyc v ih v il t dh t dsu t cwl t ct t ct t cwh v ih v il v il v ih v ih t dcar v oh v ih v ih v il t esu t cm t dcar v ol t esu v il cl1 cl2 dl (dr) cl1 cl2 car e m 123 77787980 76 v il free datasheet http://www..net/


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